1. Field of the Invention
The present invention relates to a semiconductor device fabrication method, and more particularly, to a bipolar semiconductor device fabrication method.
2. Background of the Related Art
Among related self-alignment techniques applicable for implementing high speed operation, U.S. Pat. No. 4,851,362 discloses a selective epitaxial layer growth and a floating base formation method to decrease a junction capacitance between a base and a collector. This method provides an ultra high speed device capable of decreasing a parasitic capacitance between the base and collector (N+ buried diffusion region) by thickening an insulation layer of a lower portion of a floating base polysilicon layer. This results in a bipolar semiconductor device fabrication technique applicable to a radio frequency semiconductor circuit.
According to the related art technique, a polysilicon base electrode layer is formed on a predetermined region of a silicon substrate, and an insulation layer is formed on side walls of the polysilicon layer. First and second epitaxial layers are selectively grown on the exposed surface of the silicon substrate to connect to the polysilicon layer. An active base and an emitter are formed in the epitaxial layers so that the epitaxial layers are used as a base pull-out electrode. The related art device operation is identical to that of a known bipolar transistor having base, emitter and collector electrodes.
However, the first epitaxial layer may become too thick, for example, as thick as an oxide layer formed below the base electrode. This thickness may cause deteriorating high speed characteristics of the device. In other words, a thin collector layer operates effectively under low power, unless the first epitaxial layer becomes too thick.
Further, when an emitter and a collector polycrystalline silicon electrode are deposited, the emitter region is opened and an unnecessary portion of the polycrystalline silicon electrode is etched, possibly causing deterioration in step coverage characteristics during subsequent metallic wiring steps.
The above references are incorporated by reference herein where appropriate for appropriate teachings of additional or alternative details, features and/or technical background.
An object of the present invention is to substantially obviate one or more of the problems, and limitations and disadvantages of the related art.
Another object of the present invention is to provide a semiconductor device fabrication method capable of improving step coverage characteristics in a metallic wiring process.
The objects of the present invention can be achieved in a whole, or in part, by forming a semiconductor device with a method that includes the steps of forming a first insulation layer and a semiconductor layer sequentially over a semiconductor substrate having a buried diffusion region. A second insulation layer is formed over the first semiconductor layer, and the second insulation layer is etched to form a mask. The first semiconductor layer and the first insulation layer are then etched, using the mask, to form first and second openings that expose predetermined portions of the substrate corresponding to the buried diffusion region. Portions of the semiconductor layer and the second insulation layer are selectively etched to expose a predetermined portion of the first insulation layer. A third insulation layer is formed over respective side walls of the exposed first semiconductor layer and the first and second openings. A first epitaxial layer is then formed over the semiconductor substrate exposed through the first and second openings. Portions of the third insulation layer are removed to expose side walls of the first semiconductor layer, and a second epitaxial layer is formed over the first epitaxial layer for connecting to the first semiconductor layer. An active base region and a second conductive type collector region are thus formed in the second epitaxial layer of the first and second openings. A second semiconductor layer is then formed over the entire structure, and portions of the second semiconductor layer are oxidized to form a fifth insulation layer. An emitter region is then formed in the active base region of the first opening. An emitter electrode, a base electrode and a collector electrode are formed over the corresponding emitter region, base region and collector region of the second semiconductor layer by a metallic wiring process.
The objects of the present invention can also be achieved in a whole, or in part, by a semiconductor device including a substrate having a buried diffusion region, a first insulation layer formed over the substrate, the first insulation layer having openings that expose portions of the buried diffusion region, and a base region including a first semiconductor layer formed over predetermined portions of the first insulation layer, and an epitaxial layer formed over an exposed portion of the buried diffusion region and adjacent the first semiconductor layer. The device also includes a collector region having an epitaxial layer formed over another exposed portion of the buried diffusion region. An emitter region is formed in the base region. Contact plugs, formed of portions of a second semiconductor layer, are formed over and connected to the base region, the collector region, and the emitter region. A base electrode, a collector electrode and an emitter electrode, are formed such that each electrode is connected to the contact plug for coupling to the base region, the collector region and the emitter region, respectively.
Additional advantages, objects, and features of the invention will be set forth in part in the description which follows and in part will become apparent to those having ordinary skill in the art upon examination of the following or may be learned from practice of the invention. The objects and advantages of the invention may be realized and attained as particularly pointed out in the appended claims.